mode-verilog.js 3.9 KB

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  1. ace.define("ace/mode/verilog_highlight_rules",["require","exports","module","ace/lib/oop","ace/mode/text_highlight_rules"], function(require, exports, module) {
  2. "use strict";
  3. var oop = require("../lib/oop");
  4. var TextHighlightRules = require("./text_highlight_rules").TextHighlightRules;
  5. var VerilogHighlightRules = function() {
  6. var keywords = "always|and|assign|automatic|begin|buf|bufif0|bufif1|case|casex|casez|cell|cmos|config|" +
  7. "deassign|default|defparam|design|disable|edge|else|end|endcase|endconfig|endfunction|endgenerate|endmodule|" +
  8. "endprimitive|endspecify|endtable|endtask|event|for|force|forever|fork|function|generate|genvar|highz0|" +
  9. "highz1|if|ifnone|incdir|include|initial|inout|input|instance|integer|join|large|liblist|library|localparam|" +
  10. "macromodule|medium|module|nand|negedge|nmos|nor|noshowcancelled|not|notif0|notif1|or|output|parameter|pmos|" +
  11. "posedge|primitive|pull0|pull1|pulldown|pullup|pulsestyle_onevent|pulsestyle_ondetect|rcmos|real|realtime|" +
  12. "reg|release|repeat|rnmos|rpmos|rtran|rtranif0|rtranif1|scalared|showcancelled|signed|small|specify|specparam|" +
  13. "strong0|strong1|supply0|supply1|table|task|time|tran|tranif0|tranif1|tri|tri0|tri1|triand|trior|trireg|" +
  14. "unsigned|use|vectored|wait|wand|weak0|weak1|while|wire|wor|xnor|xor" +
  15. "begin|bufif0|bufif1|case|casex|casez|config|else|end|endcase|endconfig|endfunction|" +
  16. "endgenerate|endmodule|endprimitive|endspecify|endtable|endtask|for|forever|function|generate|if|ifnone|" +
  17. "macromodule|module|primitive|repeat|specify|table|task|while";
  18. var builtinConstants = (
  19. "true|false|null"
  20. );
  21. var builtinFunctions = (
  22. "count|min|max|avg|sum|rank|now|coalesce|main"
  23. );
  24. var keywordMapper = this.createKeywordMapper({
  25. "support.function": builtinFunctions,
  26. "keyword": keywords,
  27. "constant.language": builtinConstants
  28. }, "identifier", true);
  29. this.$rules = {
  30. "start" : [ {
  31. token : "comment",
  32. regex : "//.*$"
  33. }, {
  34. token : "comment.start",
  35. regex : "/\\*",
  36. next : [
  37. { token : "comment.end", regex : "\\*/", next: "start" },
  38. { defaultToken : "comment" }
  39. ]
  40. }, {
  41. token : "string", // " string
  42. regex : '".*?"'
  43. }, {
  44. token : "string", // ' string
  45. regex : "'.*?'"
  46. }, {
  47. token : "constant.numeric", // float
  48. regex : "[+-]?\\d+(?:(?:\\.\\d*)?(?:[eE][+-]?\\d+)?)?\\b"
  49. }, {
  50. token : keywordMapper,
  51. regex : "[a-zA-Z_$][a-zA-Z0-9_$]*\\b"
  52. }, {
  53. token : "keyword.operator",
  54. regex : "\\+|\\-|\\/|\\/\\/|%|<@>|@>|<@|&|\\^|~|<|>|<=|=>|==|!=|<>|="
  55. }, {
  56. token : "paren.lparen",
  57. regex : "[\\(]"
  58. }, {
  59. token : "paren.rparen",
  60. regex : "[\\)]"
  61. }, {
  62. token : "text",
  63. regex : "\\s+"
  64. } ]
  65. };
  66. this.normalizeRules();
  67. };
  68. oop.inherits(VerilogHighlightRules, TextHighlightRules);
  69. exports.VerilogHighlightRules = VerilogHighlightRules;
  70. });
  71. ace.define("ace/mode/verilog",["require","exports","module","ace/lib/oop","ace/mode/text","ace/mode/verilog_highlight_rules","ace/range"], function(require, exports, module) {
  72. "use strict";
  73. var oop = require("../lib/oop");
  74. var TextMode = require("./text").Mode;
  75. var VerilogHighlightRules = require("./verilog_highlight_rules").VerilogHighlightRules;
  76. var Range = require("../range").Range;
  77. var Mode = function() {
  78. this.HighlightRules = VerilogHighlightRules;
  79. this.$behaviour = this.$defaultBehaviour;
  80. };
  81. oop.inherits(Mode, TextMode);
  82. (function() {
  83. this.lineCommentStart = "//";
  84. this.blockComment = {start: "/*", end: "*/"};
  85. this.$id = "ace/mode/verilog";
  86. }).call(Mode.prototype);
  87. exports.Mode = Mode;
  88. });